IBM Unveils 0.7-Nanometer Chip Tech With 50% Higher Performance

3 articles · Updated · O'Reilly Media · Jul 10

IBM said its new 0.7-nanometer chip technology can fit about 100 billion transistors on a fingernail-sized chip, marking what it calls the world’s first sub-1 nanometer breakthrough.
50% higher performance and 70% lower power use versus the prior 2-nanometer generation come from pushing transistor scaling toward physical limits and stacking components vertically.
The advance is still a research milestone rather than a commercial product, but it underscores how AI infrastructure is shifting from model size to hardware efficiency, power and cooling.
OpenAI and Broadcom’s inference-focused Jalapeño chip and Nvidia’s 45°C liquid-cooled AI factory design point to the same trend: physical infrastructure is becoming the next battleground in AI.

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O'Reilly Media3h ago

IBM Unveils World's First Sub-1 Nanometer Chip Technology

Reuters3h ago

IBM unveils tech for chip smaller than 1 nanometer in AI computing push | Reuters

The National3h ago

IBM introduces 'first sub-1 nanometre chip' technology | The National

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IBM's 0.7nm Nanostack Breakthrough: Ushering in the Next Era of High-Density, Energy-Efficient Chips

Overview

IBM has recently announced a major breakthrough in semiconductor technology by achieving sub-1 nanometer chip density, specifically 0.7 nm, using its innovative Nanostack architecture. This design stacks two transistors, each made from ultra-thin nanosheets, directly on top of each other, with each nanosheet measuring about 5 nanometers thick. By bonding these layers vertically, IBM achieves significant compression of density and a dramatic reduction in chip size. This approach promises increased performance and energy efficiency, marking a crucial step forward for the future of powerful and compact processors.

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