Sub-1% single-qubit gate error rates were achieved on Intel’s Tunnel Falls six-dot device using “quasi-zero” pulses, matching conventional filtered-control performance with fewer calibration parameters.
Near-zero time-integral pulse designs cancel signal distortions that normally require complex transfer-function modeling, while a small residual offset preserves enough control authority for accurate gates.
The pulses kept the same duration as traditional filtered pulses, avoiding a speed penalty that could worsen decoherence, and the approach was benchmarked in simulation and hardware across complete gate sets.
Calibration simplification matters because tuning effort rises non-linearly with qubit count, though the team said scaling to larger arrays still faces risks from crosstalk, negative-pulse charge effects and device-to-device variation.
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Breaking the 1% Barrier: Quasi-Zero Pulses Revolutionize Quantum Gate Fidelity and Calibration
Overview
On June 29, 2026, Q-CTRL and Intel achieved a major milestone by reducing quantum gate errors to below 1% on Intel’s Tunnel Falls silicon quantum dot device. This breakthrough was made possible by the innovative use of 'quasi-zero' pulse designs, which allowed for precise control over quantum states while minimizing unwanted interactions and noise. As a result, the team achieved high-fidelity quantum gates, making it easier to scale up quantum systems and perform complex computations. The quasi-zero pulse method also matched the fidelity of traditional techniques but required fewer calibration parameters, streamlining the path toward practical, fault-tolerant quantum computers.