SMIC N+3 Matches TSMC N6 Density at 113.4 MTr/mm² as Huawei Turns to 3D Stacking
Updated
Updated · odaily.news · Jun 15
SMIC N+3 Matches TSMC N6 Density at 113.4 MTr/mm² as Huawei Turns to 3D Stacking
2 articles · Updated · odaily.news · Jun 15
Summary
113.4 MTr/mm² is the key teardown finding: SemiAnalysis said SMIC’s N+3 node slightly tops TSMC N6’s 107.7 MTr/mm² despite using DUV rather than EUV.
32.5nm minimum metal pitch helps deliver that density, but SemiAnalysis said SMIC relies on costly SAQP multi-patterning, raising process complexity, yield risk and per-chip cost versus TSMC’s simpler N6 flow.
Kirin 9030 shows the trade-off in products: its GPU roughly matches 2022 flagship chips, while its big-core IPC sits near the 2021 Cortex-X2 and trails Apple’s latest M5 by about 2.7x in absolute performance.
5GHz by 2031 is Huawei’s target under its LogicFolding roadmap, which uses 3D vertical stacking to shorten interconnect paths and pursue an equivalent 295 MTr/mm² density.
Export controls are reshaping rather than stopping China’s chip push, with SMIC know-how spreading to other domestic players and CXMT memory already appearing in Huawei’s flagship supply chain.