Illinois Researchers Stack 3 Silicon Layers for Denser Chips as Moore's Law Slows
Updated
Updated · Interesting Engineering · May 30
Illinois Researchers Stack 3 Silicon Layers for Denser Chips as Moore's Law Slows
4 articles · Updated · Interesting Engineering · May 30
Three stacked silicon layers with 625 transistors each were built directly atop one another, demonstrating monolithic 3D chips with performance comparable to standard silicon devices.
A sub-200°C bonding process using ultrathin single-crystalline silicon nanomembranes solved the key heat problem, keeping added layers below the roughly 400°C limit that would damage existing circuitry.
Yields reached 98% to 100%, and the team linked the layers with vertical metal connections to show working 3D logic circuits and SRAM cells.
Unlike commercial 3D chips that bond separately made wafers, the monolithic approach enables denser vertical connections, shorter on-chip communication paths and better energy efficiency.
The Nature study points to a path beyond transistor shrinkage, and the researchers are now working with IBM, Intel and TSMC to move the process into a foundry.
As transistors stack into skyscrapers, can chipmakers defeat the intense heat threatening to melt Moore's Law's future?
Beyond the lab, how soon could these stacked 3D chips supercharge the AI revolution inside our data centers?
Breakthrough in 3D Silicon Stacking: Illinois Team Achieves High-Yield, Low-Temperature Triple-Layer Chips for Next-Gen Computing
Overview
A major breakthrough by Professor Qing Cao's team at the University of Illinois Urbana-Champaign introduces a scalable, low-temperature method for stacking three layers of high-performance silicon circuits, overcoming long-standing thermal and material barriers in chip manufacturing. This innovation achieves near-perfect yields and prevents damage to previously fabricated layers, addressing the challenges faced as traditional 2D scaling and Moore's Law slow down. As the semiconductor industry approaches the physical and economic limits of planar integration, this practical 3D chip technology offers a promising path forward for denser, more powerful, and energy-efficient computing.